1. Field of Invention
The present invention relates to semiconductor devices, and more particularly to a lateral power MOSFET.
2. Description of Related Art
The development of single chip processes for integrating power switches with control circuitry is a major trend in the field of power IC development. The LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs. The LDMOS process involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction. Since the lateral MOSFET is manufactured using a typical IC process, the control circuit and the lateral power MOSFET can be integrated onto a monolithic power IC.
FIG. 1 shows a block diagram of a power converter. A transformer 200 is the load of a monolithic power IC 500. A LDMOS transistor 100 having a drain electrode 10, a source electrode 20 and a polysilicon gate electrode 40 is used to switch the transformer 200. A resistor 400 is utilized to sense a switching current Is of the LDMOS transistor 100 for power control. A controller 300 generates a control signal to drive the LDMOS transistor 100 for power conversion. In order to reduce the cost and optimize switching performance, the controller 300 and the LDMOS transistor 100 are implemented on the same substrate. The LDMOS process employing a reduced surface electric field (RESURF) technique using low thickness of EPI or N-well can achieve a high voltage with low on-resistance.
Recently, development of high-voltage LDMOS transistors have been proposed by Klas H. Eklund, in U.S. Pat. No. 4,811,075 entitled “High Voltage MOS Transistors”; by Vladimir Rumennik and Robert W. Busse, in U.S. Pat. No. 5,258,636 entitled “Narrow Radius Tips for High Voltage Semiconductor Devices with Interdigitated Source and Drain Electrodes”; However, the drawback of theses prior arts are that aforementioned LDMOS transistor have higher on-resistance. High voltage and low on-resistance LDMOS transistor, for example, are proposed by Klas H. Eklind, in U.S. Pat. No. 5,313,082 entitled “High Voltage MOS Transistor with a Low On-Resistance”; by Gen Tada, Akio Kitamura, Masaru Saito, and Naoto Fujishima, in U.S. Pat. No. 6,525,390 B2 entitled “MIS Semicondiictor Device with Low On Resistance and High Breakdown Voltage”; by Vladimir Rumennik, Donald R. Disney, and Janardhanan S. Ajit, in U.S. Pat. No. 6,570,219 B1 entitled “High-voltage Transistor with Multi-layer Conductor Region”; by Masaaki Noda, in U.S. Pat. No. 6,617,652 B2 entitled “High Breakdown Voltage Semiconductor Device”. Although a high voltage and low on-resistance LDMOS transistor can be manufactured, the complexity of the production processes increases the production cost and/or reduces the production yield. Another disadvantage of these proposed transistors is none-isolated source structure. A none-isolated transistor current could flow around the substrate. This may generate noise interference in the control circuit 300. Besides, the switching current Is of the LDMOS transistor 100 can generate a ground bounce to disturb the control circuit 300. Furthermore, only an isolated LDMOS transistor can restrict the current flow. Therefore the switching current Is through the resistor 400 can be accurately measured. In order to solve these problems, the present invention proposes a LDMOS structure to achieve a high breakdown voltage, low on-resistance and isolated transistor for the monolithic integration.